Analog Circuit Design for Process Variation-Resilient by Marvin Onabajo

By Marvin Onabajo

This ebook describes numerous suggestions to handle variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The equipment awarded are effects from contemporary examine works regarding receiver front-end circuits, baseband clear out linearization, and information conversion. those circuit-level strategies are defined, with their relationships to rising system-level calibration ways, to music the performances of analog circuits with electronic tips or regulate. assurance additionally contains a technique to make the most of on-chip temperature sensors to degree the sign strength and linearity features of analog/RF circuits, as confirmed through attempt chip measurements.

  • Describes numerous variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
  • Includes integrated trying out concepts, associated with present business trends;
  • Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch relief approaches;
  • Describes theoretical suggestions in addition to experimental effects for attempt chips designed with variation-aware techniques.

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Extra resources for Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

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Current trends show that the conglomerate of analog and digital techniques is crucial for effective built-in tests of complex single-chip systems, motivating the continued development of BITs and digitally controllable analog circuit blocks. 2. 6 High-Volume Manufacturing Testing A production test strategy for transceiver systems-on-a-chip has recently been proposed in [34] to address cost savings through the use of soft specification limits based on statistical parameter distributions in combination with a defect-oriented test approach that enables low-cost testing using less accurate equipment or builtin circuitry.

IEEE J. Solid-State Circuits 44(2), 495–508 (2009) 41. M. Miyazaki, G. Ono, K. 2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J. Solid-State Circuits 37(2), 210–217 (2002) 42. A. W. L. A. M. Khellah, A. M. Geuskens, C. B. Wilkerson, T. K. De, A 45 nm resilient microprocessor core for dynamic variation tolerance. IEEE J. Solid-State Circuits 46(1), 194–208 (2011) 43. -B. Kim, K. K. Kim, J. Doyle, A CMOS low power fully digital adaptive power delivery system based on finite state machine control, in Proceedings of IEEE International Symposium Circuits and Systems (ISCAS), May 2007, pp.

2 is Rc = (R/4)Á(1+6Co/C). To ensure high linearity with variations of parasitic capacitances, the programmable range of Rc is selected based on process corner simulations as described in Sect. 4. 2 V supply. Attenuators k1, (1 - k1), and k2 are realized with floating-gate devices for attenuation-predistortion linearization of this fullydifferential topology. The gates (G) of the standard NMOS transistors in the OTA core are not resistively biased and are only connected to two conventional metalinsulator-metal (MIM) capacitors.

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